1. Field of the Invention
The present invention relates to a wide band gap semiconductor device used in inverters, switching power supplies, and other power devices, in particular to wide band gap semiconductor devices for switching operation at high frequencies.
2. Description of the Related Art
Wide band gap semiconductors including silicon carbide (SiC) semiconductor (hereinafter also referred to as “SiC”), gallium nitride (GaN) semiconductor (hereinafter also referred to as “GaN”), and diamond are expected for application to power devices owing to their excellent properties such as high breakdown electric field strength and high thermal conductivity.
FIG. 4 is a schematic sectional view of a part of a vertical power MOSFET of SiC according to a conventional technology. This SiC vertical power MOSFET has a low impurity concentration n type drift layer 2 (hereinafter “low impurity concentration” is simply referred to as “low concentration”) deposited by epitaxial growth on a high concentration n type semiconductor substrate 1. A plurality of p channel regions 3 is selectively disposed in parts of the surface region of the low concentration n type drift layer 2. Under the p channel region 3, a high concentration p base region 4 is provided to prevent the p channel region 3 from punching through when the pn junction between the p channel region 3 and the low concentration n type drift layer 2 is subjected to a high reverse bias voltage. In parts of the surface region of the p channel region 3 are disposed an n+ source region 5 and a p+ contact region 6 for connecting the high concentration p base region 4 with a source electrode 9, which is mentioned below, with low resistance. A gate electrode 8 of conductive poly-silicon covers the surface region of the low concentration n type drift layer 2 and the p channel regions 3 between the n+ source region 5 and the surface region of the n− drift layer 2. The gate oxide film 7 is intercalated beneath the gate electrode 8. The source electrode 9 is in contact with the surfaces of the n+ source region 5 and the p+ contact region 6. A drain electrode 10 is in contact with the other surface of the high concentration n type semiconductor substrate 1. An interlayer dielectric film (not shown in the figure) is provided between the poly-silicon gate electrode 8 and the source electrode 9.
The following describes a basic operation of the SiC vertical power MOSFET of FIG. 4. When a voltage over a threshold value is applied onto the poly-silicon gate electrode 8 with respect to the source electrode 8, an inversion layer is formed in the surface region of the p channel region 3 right under the poly-silicon gate electrode 8. If a positive voltage is applied onto the drain electrode 10 with respect to the source electrode 9 under this condition, an electron pathway is formed consisting of: source electrode 9—n+ source region 5—the inversion layer in the surface region of the p channel region 3—the n− type drift layer 2—the high concentration n type semiconductor substrate 1—the drain electrode 10. As a result, an electric current flows from the drain electrode 10 to the source electrode 9, which is an ON state. If the voltage applied to the poly-silicon gate electrode 8 is lower than the threshold value with respect to the source electrode 9, the inversion layer disappears and the current does not flow, which is an OFF state. This basic operation does not differ from usual MOSFETs of silicon semiconductor (simply referred to as “Si”). However, the wide band gap semiconductors exhibit a material property of higher breakdown electric field strength than that of Si: 10 times as high for 4H—SiC, 11 times as high for GaN, and 19 times as high for diamond as the Si. As a consequence, a low concentration n type drift layer 2 of a wide band gap semiconductor can have a high impurity concentration and a small thickness as compared with a Si device. In other words, a high withstand voltage and a low ON state resistance can be achieved.
FIG. 5 shows a relationship between withstand voltage and minimum ON state resistance in comparison between the Si and 4H—SiC, in which the abscissa represents the withstand voltage and the ordinate represents ON resistivity for unit area (1 cm2). Thus, FIG. 5 shows a relationship between the withstand voltage and the theoretically minimum ON state resistance of a MOSFET disregarding channel resistance and contact resistance with electrodes. These relationships are generally referred to as Si limit and SiC limit. FIG. 5 shows that the ON resistivity is proportional to the 2.5th power of the withstand voltage. The concentration and thickness of a drift layer of an SiC-MOSFET are usually designed at the values corresponding to the minimum resistivity value. For example, an SiC drift layer of a device that requires a withstand voltage of 1,200 V in consideration of some tolerance is designed with a concentration of 1.3×1016 cm−3 and a thickness of about 10 μm, and an SiC drift layer of a device that requires a withstand voltage of 1,700 V is designed with a concentration of 8×1015 cm−3 and a thickness of about 12 μm. FIG. 5 shows that an ON resistivity of 4H—SiC is theoretically about 1/1,000 of that of Si at the same withstand voltage. This is based on the fact that the breakdown electric field strength of SiC is ten times that of Si. This means, under a theoretical ultimate condition, that an SiC device, as compared with a Si device, can have a concentration in drift layer thereof of about 100 times and a thickness of about 1/10.
Some documents are known to disclose the impurity concentration of a drift layer of a vertical SiC-MOSFET. Patent Document 1 (identified further on) discloses that a drift layer epitaxially grown on an SiC semiconductor substrate in an SiC semiconductor device of a MOSFET for withstand voltage of 1,400 V preferably has a high resistivity such as would be attained by doping an n type impurity, for example nitrogen, at a concentration in the range from 1×1015 cm−3 to 1×1016 cm−3. Patent Document 2 (identified further on) discloses a method of manufacturing an n type channel SiC MOSFET in which an SiC drift layer is epitaxially grown on the surface of an n type low resistivity SiC semiconductor substrate. This drift layer has an n type impurity concentration in the range from 1×1013 cm−3 to 1×1018 cm−3 obtained by means of CVD and has a thickness in the range from 4 μm to 200 μm.